Overview

In January 1999 a start-up company named Transmeta released a processor, named Crusoe, with an architecture quite unlike any other in the market. The chip is compatible with the x86 architecture pioneered by Intel but combines a VLIW Core and unique code morphing software. This enabled Crusoe to provide a low power, high performance solution ideal for laptops, PDA's and other devices in the so-called IA (information appliance) age.

Note that although a lot of magazines/websites emphasise low power processor's in laptops, the amount of power consumed by a CPU is negligible compared to the power the screen uses. Therefore the average power of the Crusoe (1.5W) is not a significant advantage over the 5W average power of a mobile PIII (both at 500MHz).

Interestingly, the CEO of Transmeta (David Ditzel) co-wrote the article The case for Reduced Instruction computer with David Patterson in the early 80's - the first paper that advocated the RISC philosophy.

Architecture

General information

There are currently three processors in the Crusoe family:

 
TM3200
TM5400
TM5600
Intended application
PDA's, embedded devices
Mobile PC's
Mobile PC's
Frequency range
333-400MHz
500-700MHz
500-700MHz
Power (Typical)(Sleep)
1W
20mW
1.5W
60mW

1.5W
60mW

L1 Cache (KB)
96
128
128
L2 Cache (KB)
0
256
512
Package
474BGA
474BGA
474BGA
Compatible Memory
SDRAM
PC66 to PC133
DDR SDRAM
PC1600 to PC2600
DDR SDRAM
PC1600 to PC2600

As the table shows the TM5600 differs from the TM5400 only in L2 cache size.

Code morphing

The native instruction set architecture of Crusoe is totally different to x86 and relies on a software layer implemented in a Flash ROM mounted next to the CPU to translate x86 instructions to the Crusoe ISA (Instruction Set Architecture).

The diagram below shows the parts of the processor whose operations are now accomplished in software - i.e. the bottom and left hand units are no longer accomplished directly in hardware (taken from www.arstechnica.com see reference 1).




This method provides excellent flexibility:

  1. Reduces transistor count on the CPU, which reduces die size and giving higher chip yields.
  2. Enables other operating systems to be emulated without changing the underlying chip architecture.
  3. Software upgrades can be done to support new instruction extensions (such as SSE2 on the Pentium IV) rather than changing the chip architecture. Transmeta are planning to provide a software upgrade every six months with performance enhancements possible as the trends in user applications change.

Disadvantages:

  1. The extra PROM slightly increases the board space required for the combination. It may be considered that this is offset by the reduced number of transistors on the CPU but as anyone who has seen a CPU die will confirm, the chip packaging is always far larger than the die anyway.
  2. 2) Current benchmarking programs don't reflect the speed of the CPU because the code morphing software takes time to configure the CPU to the application being used. If benchmarks such as SPECInt2000 or SPECFp2000 are run then they show around a 15% improvement on the second pass - when the core is already configured to run the software.

The code morphing is similar in some ways to the way Intel/AMD change x86 instructions into micro-ops that are executed by the RISC core on the Intel P6 family (Pentium Pro, Pentium II/III and Celaron) and AMD K7 family.

Also, it must be remembered that although the hardware has been reduced and work moved to software, this software still has to be executed somewhere - and of course the only place this can be done is the CPU core.

The most important thing to remember about Crusoe is that although there is less logic it has to do more work, which makes the processor slower.

Crusoe trades speed for power consumption!