[Dade]

Not strictly related to GPUs but most people working on GPGPU computing are in the HPC field so you may be interested.

There is a new project looking for money on Kickstart: http://www.kickstarter.com/projects/...r-for-everyone

With the the HPC scene pretty much dominated by GPUs (i.e. SIMD or SIMT or whatever they are called today), trying a pure MIMD route could be interesting. Porting existing applications will still not be a trivial task (i.e. Parallella looks a lot like the old Transputer) but it could be a lot easier than with SIMD.

[Grall]

They have a very wonky way of counting chip performance by adding up the clock speed of all the processor cores. That's just not proper, from any point of view.

[Brad Grenz]

The performance per watt and price don't seem that impressive.

[pcchen]

Its off-chip bandwidth seems to be just too low. Of course, such project is probably still good for people to experiment with MPI or OpenMP (i.e. not for real works, but can learn how to do proper parallel programming).

[Alexko]

Originally Posted by Grall

They have a very wonky way of counting chip performance by adding up the clock speed of all the processor cores. That's just not proper, from any point of view.

Yeah, that was a forgivable marketing misstep in the early days of dual-core processors, when conveying the advantage of a dual-core was deemed difficult, but now it just makes them look amateurish and really hurts their credibility.

[Simon F]

Originally Posted by Dade

(i.e. Parallella looks a lot like the old Transputer)

oooh. Deja vu indeed.

[fellix]

Originally Posted by Grall

They have a very wonky way of counting chip performance by adding up the clock speed of all the processor cores. That's just not proper, from any point of view.

That reminds me of the times, when Intel competitors were slapping the silly "P-rating" numbers all over the place.

[Exophase]

If you think their MHz added numbers you should look at the performance "comparison" video they made:

http://www.youtube.com/watch?feature...&v=4sMWbaV1sRQ

I think this could be the worst benchmark test I've ever seen.

As for the actual product.. can anyone think of any applications where pure MIMD is a win, but only with 32KB of fast memory per core, and an emphasis on single-precision floating point arithmetic? It would be interesting to learn more about their core uarch, but unfortunately you're told to contact their sales division if you want their hardware manual (way to put your first foot forward in embracing that open hardware philosophy you go on about on your KS page guys). They do say somewhere that it's superscalar; I wonder if this is a simple VLIW. You'd have to think that the alleged power budget allocated for these cores wouldn't allow for much, if anything in the way of branch prediction, so I doubt they'd be any good at general purpose code even if it did exhibit extreme and explicit memory locality.

[McHuj]

I think you guys would be surprised how often companies add up MHz. I've seen it at least in two different companies now. They're both in the signal processing fields so it maybe specific to that industry,

From my experience, these types of processors are a good match for prototyping work of signal processing tasks. For example in a wireless receiver you may have a very simple processing chain look like: resampler->FFT->Channel Estimate->Equalizer->Symbol Demapper->Decoder. In theory, you can parallelize those components and map the whole chain onto the processor. This approach is basically FPGA like, but written in C (year right, it's all ASM) instead of RTL. If you can actually run your tasks in real time, you can actual test your performance before taping out an ASIC. Many companies do this by running the ASIC RTL on FPGA. For a final product I don't think this makes sense.

However, if a task is highly parallel and requires a lot of processors, you are better off using one processor with a wide SIMD vector since it will be much more power efficient. Chances are that a task spread out over a whole processor like this will be bottlenecked by the interprocessor communications network. If that communication isn't deterministic, well, good luck both debugging and designing it in way that it works efficiently without overhead.

If you're tasks are serial, chances are they will be the bottlenecked by the single thread performance of each core. It's doubtful these types of cores are powerful at all.

Without a revolutionary BW/Shared memory innovation, I don't think these things will ever work. Transputer right.

[Vitaly Vidmirov]

Originally Posted by Exophase

It would be interesting to learn more about their core uarch

So far the most detailed description is here:
http://www.adapteva.com/wp-content/u...apteva_mpr.pdf

[Dade]

Originally Posted by Vitaly Vidmirov

So far the most detailed description is here:
http://www.adapteva.com/wp-content/u...apteva_mpr.pdf

Thanks, the paragraph "Silicon on a Shoestring Budget" is interesting a funny to read, I had no idea it was possible to develop a CPU with such a little amount of resources.

[Exophase]

Originally Posted by Vitaly Vidmirov

So far the most detailed description is here:
http://www.adapteva.com/wp-content/u...apteva_mpr.pdf

Thanks, that was pretty thorough. Like I suspected, branch prediction is minimal. I wonder if the pipeline is has interlocks at all, or if everything produces delay slots. I also wonder what the efficiency of this is like vs a multicore VLIW FP DSP like C67x. I guess the big power and area savings comes in the lack of cache and the way the memory is laid out. They're actually specifically positioning this for DSP tasks - surely explicit parallelism of some form (be it SIMD or VLIW) is a win there? Does having a bunch of fully independent scalar cores really help you?

Actually, what I really wonder is how it compares with Ziilabs stemcell array SoCs, because on paper it looks pretty similar, although it appears to have a somewhat different core interconnect topology.

[codedivine]

Epiphany architecture reference manuals released.
http://www.kickstarter.com/projects/...everyone/posts

I have backed the project. I am actually pretty excited about this.

[3dcgi]

Why are you excited about it?

[Dade]

Originally Posted by 3dcgi

Why are you excited about it?

Because:

- it is a MIMD (and not a SIMD like all GPUs). It can solve some kind of problem a lot better than GPUs even with a lower peak performance.

- it has an extremely good GFLOPS/Watt ratio.

- the dies size is 2mm^2 (the guessed die size of a AMD 7970 is 354mm^2). There is a lot of room for improvements.

- it usable in many embedded applications where GPUs aren't very practical because of their size/cooling/power requirements. Good luck installing a Fermi GPU in a small drone.

- they want to open source all the software.

- you can buy one at 99$ and you get a complete PC (ethernet, usb, hdmi, etc.) capable to run Ubuntu and where you can test OpenCL, etc. applications. It has a great educational value.

[Simon F]

Originally Posted by Dade

Because:

- it is a MIMD (and not a SIMD like all GPUs)

Some GPUs are MIMD.

[Dade]

Originally Posted by Simon F

Some GPUs are MIMD.

I'm not aware of any GPU recently manufactured by AMD/NVIDIA/Intel and base on a MIMD architecture. Is there something available for mobile platforms ?

[Davros]

If this is a supercomputer why are they showing benchmarks comparing it to a cortex A9 ?

[Gerry]

Originally Posted by Dade

I'm not aware of any GPU recently manufactured by AMD/NVIDIA/Intel and base on a MIMD architecture. Is there something available for mobile platforms ?

Who else makes GPUs other than those companies? Someone Simon could be closely associated with?

[Alexko]

Originally Posted by Dade

I'm not aware of any GPU recently manufactured by AMD/NVIDIA/Intel and base on a MIMD architecture. Is there something available for mobile platforms ?

Even a GCN CU is MIMD:



And Tahiti has 32 CUs running simultaneously. It just happens to be SIMD on top of it.

It's MIMerD: Multiple Instructions, Multipler Data

[McHuj]

I do like they're way of addressing data. My previous experience with stuff like this required MPI and it was a nightmare to manage the data. Data partitioning and movement had the potential to be as hard, if not harder, to handle efficiently in software than the partitioning of the operations.

I do wonder how efficient the system is when all processors are loaded and you're hitting memory from all over the chip.

[CouldntResist]

Originally Posted by Simon F

Some GPUs are MIMD.

In those MIMD GPUs, the "I" stands for vector instruction, and the "D" stands for vector data. So it's not the same MIMD I was taught in school.