NVIDIA Fermi: new GPU architecture, starting with GF100
Wednesday 30th September 2009, 11:43:00 PM, written by Rys
At their Graphics Technology Conference earlier this evening, NVIDIA announced their next-generation graphics architecture, codenamed Fermi. Graphics seems like it's not the primary focus of the first implementation of Fermi, though, with GF100 going for everyone else's jugular in the general purpose GPU compute industry.
With a brand new shader core, Fermi's compute clusters comprise a single shader multiprocessor (SM) this time. Each SM is capable of dual issuing two independent instructions per clock to two different warps, across two clocks, with each instruction run by a 16-way SIMD block capable of single precision FMAs at full rate, and doubles at half rate.
The memory heirarchy is new, with a new coherent and unified L2 cache serving all SMs with no partitions, and a new unified memory space allows each SM to talk to not just it's own local registers and shared memory, but L2 and beyond, all the way out into system memory (up to 1 TiB, backed by a hardware TLB).
Various other compute-friendly facets of performance are improved versus their last Tesla architecture chips, with GT200/T10 the pinnacle at the moment. Atomic instruction throughput is up, everything is backed by ECC, and the hardware can sustain peak SP and DP FMA instruction throughput.
We've got a short look at GF100, including speculation on some of the graphics features, in the forums, pending a proper look at things, and our friends at The Tech Report and Real World Tech have pieces talking about things, by virtue of early briefings.
With a brand new shader core, Fermi's compute clusters comprise a single shader multiprocessor (SM) this time. Each SM is capable of dual issuing two independent instructions per clock to two different warps, across two clocks, with each instruction run by a 16-way SIMD block capable of single precision FMAs at full rate, and doubles at half rate.
The memory heirarchy is new, with a new coherent and unified L2 cache serving all SMs with no partitions, and a new unified memory space allows each SM to talk to not just it's own local registers and shared memory, but L2 and beyond, all the way out into system memory (up to 1 TiB, backed by a hardware TLB).
Various other compute-friendly facets of performance are improved versus their last Tesla architecture chips, with GT200/T10 the pinnacle at the moment. Atomic instruction throughput is up, everything is backed by ECC, and the hardware can sustain peak SP and DP FMA instruction throughput.
We've got a short look at GF100, including speculation on some of the graphics features, in the forums, pending a proper look at things, and our friends at The Tech Report and Real World Tech have pieces talking about things, by virtue of early briefings.
Tagging
nvidia ± fermi, dx11, gf100
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